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2.4GHz 802.11b Zero-IF Transceivers
Table 7b. Receive Settings Register (RECEIVE), (MAX2820A/MAX2821A Only)
ADDRESS
0100
DATA BIT
D11:D9
D8:D6
D5:D3
D2:D0
CONTENT
2C (2:0)
1C (2:0)
X
X
DEFAULT
111
111
010
010
DESCRIPTION
VGA DC Offset Nulling Parameter 2
VGA DC Offset Nulling Parameter 1
Reserved — Set to these Values
Reserved — X = Don ’ t Care. Rx filter is not programmable.
Table 8. Transmit Settings Register (TRANSMIT)
ADDRESS
DATA BIT
D11:D4
CONTENT
X
DEFAULT
X
Reserved
DESCRIPTION
PA Bias Select:
0101
D3:D0
PA(3:0)
0000
?
?
?
1111 = Highest PA bias
…………
0000 = Lowest PA bias
However, the filter frequency and detector can be modi-
fied if desired. Do not reprogram VGA DC offset nulling
parameters. These settings were optimized during devel-
opment. See Table 7 for a description of the bit settings.
Transmitter Settings Register
The transmitter settings register (TRANSMIT) controls
the 4-bit PA bias DAC. The 4 bits correspond to a PA
bias current between 0 and full scale (~300μA). See
Table 8 for the bit settings.
Applications Information
Receive Path
LNA
The RX_RF inputs are high-impedance RF differential
inputs AC-coupled on-chip to the LNA. The LNA inputs
require external impedance matching and differential to
single-ended conversion. The balanced to single-
ended conversion and interface to 50 ? is achieved
through the use of an off-chip 2:1 balun transformer,
such as the small surface-mount baluns offered by
Murata and TOKO. In the case of the 2:1 balun, the RX
RF input must be impedance-matched to a differen-
tial/balanced impedance of 100 ? . A simple LC network
is sufficient to impedance-match the LNA to the balun.
The Typical Application Circuit shows the balun, induc-
tors, and capacitors that constitute the matching net-
work. Refer to the MAX2820/MAX2821 EV kit schematic
for component values of the matching network.
The line lengths and parasitics have a noticeable impact
on the matching element values in the board-level circuit.
Some empirical adjustment of LC component values is
likely. Balanced line layout on the differential input traces
is essential to maintaining good IP2 performance and RF
common-mode noise rejection.
The receivers have two LNA gain modes that are digitally
controlled by the logic signal applied to RF_GAIN.
RF_GAIN high enables the high-gain mode, and
RF_GAIN low enables the low-gain mode. The LNA gain
step is nominally 30dB. In most applications, RF_GAIN is
connected directly to a CMOS output of the baseband
IC, and the baseband IC controls the state of the LNA
gain based on the detected signal amplitude.
Receiver Baseband Lowpass Filtering
The on-chip receive lowpass filters provide the steep
filtering necessary to attenuate the out-of-band
(>11MHz) interfering signals to sufficiently low levels to
preserve receiver sensitivity. The filter frequency
response is precisely controlled on-chip and does not
require user adjustment. In the MAX2820/MAX2821, a
provision is made to permit the -3dB corner frequency
and entire response to be slightly shifted up or down in
frequency. This is intended to offer some flexibility in
trading off adjacent channel rejection vs. passband
distortion. The filter -3dB frequency is programmed
through the serial interface. The specific bit setting vs.
-3dB frequency is shown in Table 7. The typical receive
baseband filter gain vs. frequency profile is shown in
the Typical Operating Characteristics .
Receive Gain Control and DC Offset Nulling
The receive path gain is varied through an external volt-
age applied to the pin RX_AGC. Maximum gain is at
V RX_AGC = 0V and minimum gain is at V RX_AGC = 2V.
The RX_AGC input is a high-impedance analog input
designed for direct connection to the RX_AGC DAC
output of the baseband IC. The gain-control range,
which is continuously variable, is typically 70dB. The
gain-control characteristic is shown in the Typical
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